1. Field of the Invention
The present invention relates to a pulse width modulation circuit (PWM) apparatus applied to for example a laser pulse generation circuit of a laser beam printer etc. which prints for example characters and graphics by changing the pulse width of a laser pulse.
2. Description of the Related Art
Today, laser beam printers are becoming increasingly important as they are printing apparatuses which can print characters and graphics with a high quality and at a high speed.
In a laser beam printer, the output information indicating characters or graphic is written on a photoconductive drum as a latent image by a laser beam. This latent image written on the photoconductive drum is printed by an electronic photographic system. For this reason, the technique of controlling the width of the pulse of the laser beam based upon the information to be printed has become one of the most important techniques for realizing a laser beam printer.
Conventionally, various pulse width modulation (PWM) circuits have been proposed as such a means for controlling the pulse width of a laser beam.
The assignee of this application previously proposed a circuit in Japanese Patent Application No. 4-210819 filed on Jul. 14, 1992, and published on Feb. 10, 1994 as Japanese Patent Publication (Kokai) No. 6-37608. The circuit generates an output pulse using a so-called reset-set type flip-flop (hereinafter referred to as an "RS-FF"). This pulse width modulation (PWM) circuit is constituted so as to be able to produce an output pulse rising or falling at any timing, and therefore it generates the set pulse and reset pulse to be supplied to the RS-FF by programmable delay circuits.
However, in this pulse width modulation circuit, the delay time of the delay gates constituting the programmable delay circuits will fluctuate due to manufacturing variations of the semiconductor integrated circuits, the environment when used, the operation temperature and the power source voltage, etc. The details will be described below.
When the delay time per stage of the delay gates becomes long, the delay time of the whole group of delay gates, which should coincide with the period of the clock pulse, becomes longer than the period of the clock pulse. As a result, even if the pulse width set up data is given so that the pulse width of the output pulse becomes slightly shorter than the maximum value, the pulse width of the actual pulse becomes longer than the ideal pulse width, or when the reset pulse is output, the set pulse of the next period is output, and so the RS-FF circuit would become unstable in state.
Contrary to this, when the delay time per stage of the delay gates becomes short, the pulse width of the output pulse becomes shorter relative to the ideal pulse width, and an empty period is produced in the pulse width, which originally should be formed over two clock periods, resulting in the fact that it becomes impossible to stably express gradations. Also, the delay times of the respective delay gates cannot be adjusted once the circuit is produced, and therefore it is also not possible to adjust the pulse width, so the circuit can only be used with a predetermined clock period.
To solve these disadvantages, the assignee of this application has proposed a pulse width modulation circuit in Japanese Patent Application No. 4-361516, filed on Dec. 29, 1992. This PWM circuit is provided with a delay time control circuit for controlling the unit delay time per stage of the delay gates based on the deviation of the phase relationship between a delay pulse, which is input from a delay gate positioned at a predetermined stage of a plurality of stages of delay gates constituting a timing generating delay circuit generating the rising and falling timings of the output pulse by inputting a set pulse and a reset pulse to a set input end and reset input end of the RS-FF circuit, and a clock pulse, which is input to the related timing generating delay circuit.
This PWM circuit has an advantage that the delay time can be controlled so as to become short where the unit delay time per stage of the delay gates has become long or to become long where the unit delay time has become short, so that stable operation not affected by manufacturing variations, the environment of use, etc. can be realized.
In this PWM circuit, however, when a clock having a period of 1/2 of the delay time of the whole delay line is input, that is, where a frequency two times larger than the clock which has been input is input, ideally it is necessary to perform feedback in a direction of decreasing the delay value, but in actuality the feedback is carried out in a direction increasing the delay value. Namely, there is a disadvantage in that the range of the operation frequency of the circuit is restricted to a range of from the minimum operation frequency to two times or lower of the minimum operation frequency.
Also, generally, a laser beam printer provides a plurality of resolutions. When an input clock frequency for a plurality of resolutions changes two times or more, a single pulse width modulation circuit can not provide the plurality of resolutions. Accordingly, so as to provide the plurality of resolution so that the clock frequency may change to two times or more, a plurality of pulse width modulation circuits must be used, and there is a disadvantage that an increase of cost is induced.
Returning to the above-mentioned pulse width modulation circuit using an RS-FF, where the pulse width modulation circuit is used for a digital copying machine or laser beam printer, when it is intended to more precisely reproduce gradations, the following disadvantage occurs in a case where an output pulse narrower than the pulse width of the control pulse is generated or two successive output pulses are generated via a slight gap.
When it is intended to generate an output pulse narrower than the pulse width of the set pulse and reset pulse to be input to the RS-FF circuit, the periods in which the set pulse and reset pulse become the high level "H" overlap, and the RS-FF circuit does not normally operate. Also, when it is intended to successively generate output pulses having a wide width, periods in which the set pulse and reset pulse become the high level "H" overlap at a connection part of the current pulse period and next pulse period, and the RS-FF circuit does not normally operate. As a result, the image quality is low at the connection part of two output pulses.
To solve these disadvantages, the assignee of the application has proposed a pulse width modulation circuit in Japanese Patent Application No. 4-360286, filed on Dec. 29, 1992. This PWM circuit is constituted in that provision is made of a priority order of the set pulse and reset pulse for controlling the RS-FF circuit generating the output pulses so that they become almost symmetrical to each other relative to the center of the pulse period and in that the priority order is changed while dividing the same to those near the center of the pulse period and those in the regions other than this, whereby the output pulse raised by the set pulse falls by the reset pulse immediately after this, and the output pulse immediately after the falling by the reset pulse rises by the set pulse immediately after this.
This PWM circuit has an advantage that an output pulse narrower than the control pulse can be generated, the RS-FF circuit normally operates, and the deterioration of the image quality can be prevented.
In the related art as shown in FIG. 1, there is therefore provided a pulse width modulation circuit which delays a control pulse CLKP input at every predetermined period by an arbitrary time via time delay means 3 and 4, inputs the delayed control pulses S1 and S2 to a set input terminal and reset input terminal of a latch means (RS-FF) 5, respectively, and modulates the pulse width of the output pulse PWM.sub.OUT output from a latch means (RS-FF) based on the control pulses S1 and S2 input to the set input terminal and reset input terminal; wherein a latch means (RS-FF) 5 is provided with a set pulse priority mode (S6="L"), giving a priority to the control pulse S1 input to the set input end with respect to the control pulse S2 input to the reset input end for a predetermined period in the predetermined period, and a reset pulse priority mode (S6="H") , giving a priority to the control pulse S2 input to the reset input end with respect to the control pulse S1 input to the set input end for a period other than the predetermined period in the predetermined period T.
Also, there is provided a pulse width modulation circuit which delays a control pulse CLKP input at every predetermined period by an arbitrary time via time delay means 3 and 4, inputs the delayed control pulses S1 and S2 to a set input terminal and reset input terminal of a latch means 5, respectively, and modulates the pulse width of the output pulse PWM.sub.OUT output from the latch means 5 based on the control pulses S1 and S2 input to the set input terminal and reset input terminal, wherein the time delay means 3 and 4 comprise a first and second delay gate groups 3 and 4 respectively corresponding to two periods corresponding to a former half and latter half of the predetermined period T; the control pulse S1 delayed by an arbitrary time by the first delay gate group 3 is output as the set pulse to the set input terminal of the latch means 5 and the control pulse S2 delayed by an arbitrary time by the second delay gate group 4 is output as the reset pulse to the reset input terminal of the latch means 5; the latch means 5 is changed over to the set pulse priority mode (S6 ="L") or the reset pulse priority mode (S6="H") by the mode switching signal S6; and the mode switching signal S6 is changed over to the reset pulse priority mode by the control pulse S5A output from the predetermined position (T/4) among a plurality of stages of delay elements constituting the first delay gate group 3 and changed over to the set pulse priority mode by the control pulse S4A output from the predetermined position (3T/4) among a plurality of stages of time delay elements constituting the second delay gate group
FIGS. 5A to 8I are waveform diagrams showing an output pulse in a combination of pulse modes of this pulse width modulation circuit.
In the FIGURES, CP (center pulse), LP (left pulse), and RP (right pulse) are pulse modes expressing the center, leftward mode, and rightward mode, respectively.
FIGS. 2A to 2C are graphs of pulse widths of the CP mode at 0% PWM, 50% PWM and 100% PWM, respectively. FIGS. 3A to 3C are graphs of pulse widths of the LP mode at 0% PWM, 50% PWM and 100% PWM, respectively. FIGS. 4A to 4C are graphs of pulse widths of the RP mode at 0% PWM, 50% PWM and 100% PWM, respectively.
A gradation is expressed by the combination of the size of dots and position of dots. In general, there are 32 to 256 (5 bits to 8 bits) sizes of the dots and three types of positions of the center, leftward, and rightward mentioned above with respect to the pulse period. By combining these modes, the printing of characters, graphics, etc. is carried out.
Also, CP (00), LP (00), and RP (00) express a case where the 8 bits of pulse width set up data PWD are all "0" and a so-called 0 percent (%) pulse output is carried out, and CP (FF), LP (FF), and RP (FF) express a case where the 8 bits of pulse width set up data PWD are all "1" and so-called 100 percent (%) pulse output is carried out. Note that the above-described "00" and "FF" indicate the data expressed by hexadecimal notation. Below, the pulse width set up data PWD will be similarly expressed by the hexadecimal notation.
In this circuit, however, due to the priority mode of the reset (RESET) and set (SET) of the RS-FF circuit, at the time when CP is moved to LP in FIG. 5 and at the time when LP is moved to LP in FIG. 6, in a period indicated by hatching in the figure, a so-called blank pulse where no pulse is generated irrespective of the fact it is a period for which the pulse must be generated is generated by ten combination pulse modes.
Similarly, at the time when RP is moved to CP in FIG. 7 and at the time when RP is moved to RP in FIG. 8, in a period indicated by hatching in the figure, a so-called offset pulse state, where a pulse is generated irrespective of the fact it is a period for which a pulse should not be generated, is generated by eight combination pulse modes.
In a digital copying machine (DPPC) and laser beam printer (LBP), the existence of the above-mentioned blank pulse and offset pulse does not become a disadvantage in general use, but exerts an adverse influence when trying to express more precise gradations.
Particularly an offset pulse generated at the time of a 0 percent (%) pulse setting, that is, at the time of non-output of a pulse, is a disadvantage, and a phenomenon occurs of dots being printed in a nonprinting part.